The invention relates to an asynchronous logic circuit.
A logic circuit of the generic type is presented, for example, in the Patent Application submitted to the German Patent Office with the official designation P 41 15 081.3 corresponding to U.S. Ser. No. 08/146,061 and constitutes a prior art in terms of PatG .sctn.3 (2)/EPC Art. 54 (3). This is a logic circuit in which a plurality of input lines is connected both to a logic block made of n-channel field-effect transistors and to a logic block which is inverse with respect thereto and consists of p-channel transistors (split transistor switch logic), in which both blocks are connected both to a precharging transistor and a charging transistor in each case and in which the transistors which are connected to the first block can be driven directly and the transistors which are connected to the other logic block can be driven indirectly via an inverter by means of an request signal, precharging taking place in a first state (low) of the request signal and charging or evaluation taking place in the second state (high) in accordance with the logic connection prescribed by the logic blocks.
The European Patent Application with the Publication Number 0 147 598 discloses a clocked differential cascade voltage switching logic system (CVS logic system) in which a first switching device and a second switching device are provided whose first outputs are connected in each case via transistors to the supply voltage and whose second outputs are connected in each case via transistors to reference potential, the second switching device being supplied with input signals which are complementary to the input signals of the first switching device and the second switching device switching through precisely when the first switching device does not switch through, and vice versa.